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Re: AD9548 SYSCLK locked but not stable

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Thanks, pkern,

> silicon number: C3(the value is strange, because the datasheet is C6)

 

>>Sounds like you have older silicon.

 

 

>>To fix the system clock problem, use the eval software to disable the system clock doubler.

 

>>Next, Write the registers in this sequence:

 

>>Write R0x0000-R0x0417 per the setup file

>>Write R0x0A01=0x20; Set user freerun mode

>>Optional: Write R0x0A02=0x02 If you want the outputs toggling before DPLL lock.)

>>Write R0x0005=0x01

>>Write R0x0A02=0x01

>>Write R0x0005=0x01

>>Read R0x0D01. It should be 0x10 after the system clock stability timer expires.

 

I follow your steps until Read R0x0D01. I can see the data firstly 0x07, then change to 0x00. So it seems that there are some problems with SYSCLK.

 

>>(If you wrote the optional step above, you should see a clock output.)

>>Write R0x0500-0x7FF per the setup file

>>Write R0x0005=0x01

>>Write R0x0A01-R0x0A10 per the setup file

>>Write R0x0005=0x01

>>(You can ignore writing to registers after R0x0A10 in the setup file.)

 

I upload the register value and stp to attached file, please check it.

 

 

Best regards.

 

Guan Jian


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