Hello Sean,
Thanks for the response.
Your estimation of the trigger voltage was correct, it is around 5V.
Perhaps my concern about the resistor values rises from misunderstanding of the device operation, but I assume that the NC operation if formed by a PMOS with an 0V gate voltage. In the configuration shown in the schematic the source voltage of the PMOS will be ~2.5V, which means Vsg = 2.5V. Now, if the threshold voltage of the internal PMOS is lower than -2.5V then the PMOS will be in cut-off. Since the datasheet doesn't provide information regarding the internal transistors I can not be sure of the resistor values.
Basically, what I'm asking is whether the device guarantees correct operation regardless of the Source/Drain/Gate voltages (as long as they are in spec of course) or should I worry about the various transistor voltages?
Thanks again,
Alex