I need to move large amount of data from external ram bank0/ bank1 through the uart in ADSP-21369, using DMA.
The platform is ez-kit and assembler.
The serial port 19 bits DMA addressing cannot get to the external memory, and therefore the only way that I found is to do two DMAs: one from the external memory to internal memory, and the other from internal memory to the uart.
Is there a better or direct way to do this job?
Thanks,
Amir
Switching transients at the inputs are expected, and should not affect the sampled result as long as they settle before the next pixel. Source impedance will have an effect on the magnitude and settling of the transients.
Yes, it is OK to disable SCLK when registers are not being configured.
I'm currently using a AD7606-4 to measure with two of it's channels the outputs from two OpAmps in the +-5V range and forward the result in the serial interface to a fiber optics receiver. However, I am having issues and I don't receive any signals from the Data outputs.
I have observed the malfuncion of the REGCAP B pin, in which I don't see any ouput while I do see it in REGCAP A (I'm using an external reference), and I don't see the correct output in REFCAPA and REFCAPB (I see 0V). I have also observed that the IC gets unusually hot, and in my board I have been having an unusually high power consumtions that causes the 5V input to be reduced to ~4.6V, which supplies the whole system.
Can anybody give me a clue? I'm happy to help with any missing info.
Thanks in advance
Is the reference voltage on CAPT/CAPB pins stable during your measurements? Also please check the supply voltages and OFFSET pin voltage. If these voltages are settled, generally it only takes about 50 to 100 clock cycles for the output values to stabilize.
I am implementing the initialization procedure for the AD9371 for our software/hardware. In the headless.c example the Arm processor is initialized and loaded from a binary file. Is this necessary every time the software initializes, or is this firmware only need to be loaded once? The example leads me to believe this must be loaded every time the software initializes. Any help would be appreciated.
Hi Support Team,
I am trying to use the EV-ADF4002SD1Z board to evaluate a PLL consisting of ADF4002+204.8MHz VCXO. I have the SDP-S board and am using the INT-N PLL Software (v7.7.4).
I am able to communicate with the SDP-S (can flash SDP LED via the GUI) and the log at the bottom of the GUI indicates that I am successfully writing registers. I am using the following write procedure (initialization latch -> function latch -> R latch -> N latch) however I am not seeing any signal at Cp and lock is not detected.
I have verified that there is a correct frequency/amplitude signal on REFIN and RFINA (feedback from the VCXO). Do you have any debug suggestions? Is the INT-N-PLL Software v7.7.4 compatible with this EVB, it seems pretty old.
The plan I would like to use has REFIN=10.24MHz. I noticed that this is below the recommended input frequency range but the slew rate on the reference clock is 3.6 kV/us, much greater than 50V/us.Is this a problem? I also tried using a REFIN of 20.48 MHz and 204.8 MHz, however still saw no output at Cp and lock not detected.
Thanks,
Nathan
Hello, can someone please provide me with the digital model for the AD9361, as referenced in the "AD9361 Digital Model Guide"? I would like to simulate the LVDS 2R/2T mode in ModelSim or Questa to verify the timing before going to hardware.
Thanks,
Mark
Hi,
No. the samples go simultaneously to both DDCs. In other words, DDC0 and DDC1 both get the same converted sample.
Thanks
Umesh
Hi Piero,
piero wrote:
...
Suppose you use S6 and the D5 and D6 LEDs to measure how long you hold down S6.
If S6 is pressed and released in a time between 200 and 500 milliseconds, turn on the D5 LED.If S6 is pressed and released over 500 milliseconds turn on D6.
With SigmaStudio you can do it?
Yes, functions like this implement more efficiently in a microcontroller. Yet, you can perform it in SigmaStudio using a Stopwatch along with some additional blocks. The exact implementation is determined by precisely how you wish the logic to behave -- please have a look at the timing diagram below, whether this is how you want the LEDs to respond to short, longer, and longest presses of S6 (once either LED is activated, it remains ON until S6 is pressed again):
Let me know if this is satisfactory.
Best regards,
Bob
In addition to what Dan said:
- if you are seeing "zynq>" in the terminal, you are not using our SD card image. Download the latest one from here: Zynq & Altera SoC Quick Start Guide [Analog Devices Wiki]
- if you are seeing "zynq-uboot>", try to restore the default u-boot environment:
env default -a
saveenv
reset
Dragos
Hi,
For the hdl side. You have 3 options to delete and ad your blocks in the design:
1. Delete what you don't use and add your IP's in the block design script (.../hdl/projects/adrv9371x/common/adrv9371x_bd.tcl); add/clean the connections between IP's, then rebuild the project. Delete this lines to remove a TX DMA: hdl/adrv9371x_bd.tcl at hdl_2016_r2 · analogdevicesinc/hdl · GitHub .
2. Overwrite the commmands from .../common/adrv9371x_bd.tcl in .../hdl/projects/adrv9371x/zc706/system_bd.tcl similar to Adding FIR filters in a fmcomms2 design [Analog Devices Wiki] , you will find in this example how to delete and to add an IP; after you are done with the changes,rebuild the project.
3. Use vivado GUI, open block design of an already build project and do your stuff...
This may help:
Building HDL [Analog Devices Wiki]
ADI Reference Designs HDL User Guide [Analog Devices Wiki]
If your logic is not instantiated in a IP add it, you have plenty examples in hdl/library/*.
Regarding the Linux question please open a new thread on Linux Software Drivers
Andrei
The issue is, that you did not update the XDC file. Take a look at this doc. (Table 1-32) And make sure that all the pin names are updated. (be aware that you going to use the HPC) The easiest way to do this, is to match the FMC pin names (first column of the table). You can look up the required FMC pins from the schematic. (first the board's, after that interposer's) You do not need to do any modifications on the tcl.pre script, if the PIN names are updated, these errors will disappear.
You should never feel sorry because you've asked questions in a support forum. I'm glad I could help.
Hi Fritz,
By default, VDD is shorted to +12V via jumper link LK4, if not shorted, VDD via J2 connector can only be supplied with a voltage up to 20V to ensure the ratings of the MOSFETS are not exceeded.
Thanks,
Glai
Thanks sripad.
But please allow me to clarify.
What you said is correct, if register 0x20 defines the "state" or value of GPO upon entering RX or TX state.
However, UG-672 states that register 0x20 defines which GPO "changes state" or toggles upon entering RX or TX state.
In fact, UG-673 even has a specific example which says
For example let Register 0x26 be 0x00 (ENSM control enabled), Register 0x27 be 0xFF (initialize all GPO pins to 1), and Register 0x20 = 0x24(toggle the GPO_1 pin in Rx and GPO_2 in Tx). When the part enters alert state, all GPO pins will become high. When the part enters Tx, only Pin GPO_2 pin will toggle low. When the part enters Rx, GPO_1 pin will toggle low.
So following your explanation and applying it to the example given,
- from alert to RX, GPO will go from 0xF to 0x2 (3 GPOs will toggle)
- from alert to TX, GPO will go from 0xF to 0x4 (3 GPOs will toggle)
which is different from what is stated on UG-673.
got it,thanks
Thank you very much, I'll check it.
Hi,
i worked with ADIS16488 inertial sensor...
about DELTA ANGLES parameter in datasheet: ±720° range, 0° = 0x0000, 1 LSB = 720°/2^15 = ~0.022°.
now i am working on ADXRS453 gyro and i used same formula to calculating DELTA ANGLES (with specify FS), but i can't find or calculate weight of 1 LSB to calculate Angle in degree.
B.R
Pouya
Hi,
what is ADXRS453 output data rate?
i think that is about 77 Hz and when i compared that with ADIS16488 gyro(about 2.46 KHz) output rate,that is so slow.
are this is related to application?
B.R
Pouya
Hi OTI,
Adding 1nF of capacitance is equivalent to adding a longer bus cable. 20 meters of added cable for example.
The 1 nF capacitance should not limit your data rate, especially as you are operating at 100 kbps low data rate.
